V-Lab @ ANDC

To design JK Master-Slave Flip-Flop design using elementary gates.

Aim

To design JK Master-Slave Flip-Flop design using elementary gates.

Apparatus

  1. One 74LS10(3-input-nand gate) IC
  2. Three 74LS00(2-input-nand gate) IC
  3. Two 5 Volt supply volatge
  4. One Clock and one not gate/inverter

Principle

Master Slave is a type of JK flip flop in which race around condition problem is removed. In this flip flop there is two stage first stage is Master and second is Slave.

Race Around Condition

Race around Condition: Toggling more than once within a clock cycle.

Race around condition can be avoided by
  1. Master Slave Topology
  2. tp < ∆t < T
  3. Edge Triggering

where,

→ tp = pulse width
→ ∆t = time interval equal to the propagation delay through two NAND gates
→ T = Time period of the pulse

JK Master Slave Circuit Diagram

How the race around condition is removed?

As shown in above Figure there is a clock(CLK) which is connected to first stage(Master) and via inverter to second stage(Slave) i.e., if clock is 1 then first stage gets 1 and second stage gets 0.
When clock is 1 at that instant stage 1 is on and stage 2 is off and when 0, stage 1 is off and stage 2 is on. And due to this action the output of first stage transferd to stage 2 when first stage is off and second stage is on and hence the race around condition is removed.

Truth Table
clk J K Q Q'
↑ 0 0 Previous
↑ 0 1 0 1
↑ 1 0 1 0
↑ 1 1 Toggle

Formula:-

To find next state
Q(n+1) = J*Q'(n) + K'*Q(n)

Where,

  • Q(n) ⇛ Previous state or output of Jk master slave
  • Q(n+1) ⇛ Next state or output of Jk master slave
  • J,K ⇛ Inputs of JK master slave

Working:-

  1. Master is positve level triggred and Slave is negative level triggred
  2. When clock pulse is one master is activate and slave is deactivated, when clock pulse goes to zero master deactivates and slave activates.
  3. For different combination of JK Truth Table shown above

Procedure

  1. To design JK Master-Slave their is requirement of one 3-input nand gate IC(74LS10) and three 2-input nand gate IC(74LS00).
  2. Connect the circuit as shown in figure.
  3. Connect 5V supply to the circuit.
  4. Turn on the supply and write the reading.
  5. And verify it from the Truth-Table.

Animation

This animation shows the working of the JK Master-Slave Flip-Flop.

Simulator

Task: Re-create the JK Master-Slave circuit by connecting the nodes. Click an output node (orange) and its valid input nodes (blue) will glow. The simulator will only activate once all 21 wires are correctly connected.

J
K
CLK
Q
Q'

Observations

First, build the circuit in the simulator. Once complete, test all J/K combinations. The table will automatically record the output.

Clock Pulse (CLK) Input (J) Input (K) Observed Output (Q) Observed Output (Q') Remarks (Condition)
↑ 0 0
↑ 0 1
↑ 1 0
↑ 1 1

Result

Please complete the "Observations" table by building the circuit and running the simulator for all four J/K combinations. The result will appear here.

Precaution

To ensure you get the correct results from the simulator, please follow these precautions. Click on each item to expand.

You must click an **orange** (output) node first. The correct **blue** (input) nodes will begin to glow, guiding your connection.

After the circuit is built, always set your desired J and K input values *before* you click the Pulse CLK button.

If you get stuck or make a mistake, use the "Reset Wires" button. This will clear all wires and restart the simulation, allowing you to try again.

To confirm the experiment, you must test all four possible input combinations *after* the circuit is complete.

References

  1. Morris, M. M., & Ciletti, M. D. (2018). Digital Design: With an Introduction to the Verilog HDL, VHDL, and SystemVerilog (6th Edition). Pearson.
  2. Floyd, T. L. (2017). Digital Fundamentals (11th Edition). Pearson.